FIG. 1 shows a known IGBT 120 with planar gate electrodes. The IGBT 120 is a device with a four-layer structure, which layers are arranged between an emitter electrode 2 on an emitter side 11 and a collector electrode 25 on a collector side 15, which is arranged opposite of the emitter side 11. An (n−) doped drift layer 8 is arranged between the emitter side 11 and the collector side 15. A p doped base layer 4 is arranged between the drift layer 8 and the emitter electrode 2. The base layer 4 is in direct electrical contact with the emitter electrode 2. An n-doped source region 7 is arranged on the emitter side 11 embedded into the planar base layer 4 and contacts the emitter electrode 2.
A planar gate electrode 31 is arranged on top of the emitter side 11. The planar gate electrode 31 is electrically insulated from the base layer 4, the first source region 7 and the drift layer 8 by a first insulating layer 34. There is a third insulating layer 38 arranged between the planar gate electrode 31 and the emitter electrode 2. On the collector side, a collector layer 9 is arranged between the drift layer 8 and the collector electrode 25.
Such a planar MOS cell design exhibits a number of disadvantages when applied to BiMOS type switch concepts. The device has high on-state losses due to a plurality of effects. The planar design offers a lateral MOS channel which suffers from carrier spreading (also called JFET effect) near the cell. Therefore, the planar cells show low carrier enhancement. Furthermore, due to the lateral channel design, the planar design also suffers from the hole drain effect (PNP effect) due to the lateral electron spreading out of the MOS channel. The region between the cells offers strong charge enhancement for the PiN diode part. This PiN effect, however, can only show a positive impact in high voltage devices with low cell packing densities (a low number of cells within an area). In order to achieve reduced channel resistance, the planar devices are made with less cell packing density, and this can only be compensated with narrow pitches (distance between two cells), thereby reducing the PiN effect.
The high losses have been reduced by the introduction of n doped enhancement layers, which surround the planar base layer.
Concerning the blocking capability, the planar design provides good blocking capability due to low peak fields in the cells and between the cells.
The planar design can have a large MOS accumulation region below the gate electrode and large associated capacitance. Nevertheless, the device shows good controllability due to the application of a field oxide type layer between the cells for miller capacitance reduction. Therefore, good controllability and low switching losses can be achieved for planar design.
Furthermore, the cell densities in planar designs can be easily adjusted for the required short circuit currents.
As a result taking all the above mentioned effects into account, known planar cells apply very narrow cells and wide pitches with Field Oxide layers.
Alternatively to planar designs, known IGBTs 130 having trench MOS cell designs as shown in FIG. 2 have been introduced, in which a trench gate electrode 3 is electrically insulated from a base layer 4, a first source region 7 and the drift layer 8 by a first insulating layer 34. The trench gate electrode 3 is arranged in the same plane and lateral to the base layer 4 and extends deeper into the drift layer 8 than the base layer 4.
With such trench gate electrode designs, the on-state losses are lower, because the trench design offers a vertical MOS channel, which provides enhanced injection of electrons in the vertical direction and suffers from no drawbacks from charge spreading (so called JFET effect) near the cell. Therefore, the trench cells show much improved carrier enhancement for lower losses. Due to the vertical channel design, the trench also offers less hole drain effect (PNP effect) due to the improved electron spreading out of the MOS channel. At the bottom of the trench, there is an accumulation layer, which offers strong charge enhancement for the PIN diode part. Hence, wide and/or deep trenches show optimum performance. The trench design offers large cell packing density for reduced channel resistance. The trench design, however, suffers from lower blocking capability near the bottom corners of the trenches due to high peak electric fields. The trench design has a large MOS accumulation region and associated capacitance with difficulty to apply field oxide type layers in the trench for miller capacitance reduction. Therefore, the device results in poor controllability and high switching losses. Furthermore, the high cell densities in trench designs will result in high short circuit currents.
In order to reduce the above mentioned effects, the trench gate electrodes have been made wide and deep, whereas the cells have to be made narrow, so that losses are reduced and short circuit current can be kept low. However, such trenches are difficult to process and will still suffer from bad controllability.
In another known concept shown in FIG. 3, IGBTs 140 having a pitched-trench gate electrode 300 design have been applied, in which a MOS area is inserted between the cells. The two trench gate electrodes 3 are connected by a layer made of the same material as the trench gate electrodes, thereby forming an area below, in which a part of the base layer is arranged, but no source region or contact of the base layer to the emitter electrode is available in this MOS area. However, such devices result in poor blocking properties and high switching losses due to slow field spreading from the pitched area during switching (FIG. 3).
In another approach shown in FIG. 4, dummy trench cells 110 have been introduced into another known IGBT 150, in which active cells 100 and dummy cells 110 are arranged in an alternating manner. The base layer 4 and first source regions 7 do not have a contact with the emitter electrode 2 in the dummy cell 110, However, similar problems to those mentioned for the pitched-trench design apply. For this design, n doped enhancement layers can be introduced between the drift layer 8 and the base layer 4 in order to reduce on-state losses.
In JP 2011-40586, another known IGBT 160 shown in FIG. 5 having trench gate electrodes is described. Between two active trenches 3, shallow pitched trenches 300 with an upper lying planar layer of the same electrically conductive poly silicon material are arranged, which do not have a contact with the emitter electrode 2 similar to the known IGBT 140 shown in FIG. 3. However, as one base layer 4 is applied in the active cells as well as in the pitched gate area below the shallow pitched trenches 300, this base layer 4 has to be rather deep because the pitched gate electrodes 300 are embedded in the base layer 4, whereas the active trenches 3 are deeper than the base layer 4. The manufacturing of such trenches 3, 300 with different depths and the deep p base layer 4 is difficult, because the active trenches 3 and the pitched trenches have to be manufactured separately. Furthermore, the deep p base layer 4 is connected to the active trenches 3, which has a negative impact on the device turn-on behaviour in terms of controllability.